National Semiconductor SC/MP
Produced-startApril 1976
Slowest1
Slow-unitMHz
Fastest4
Fast-unitMHz
Manuf 1National Semiconductor
Data-width8 bits
Address-width16 bits
Pack 140-pin DIP
SuccessorSC/MP II (INS8060)
70-Series (INS807x)

National Semiconductor's SC/MP (pronounced scamp) for Simple Cost-effective Micro Processor, is an early 8-bit microprocessor which became available in April 1976. It was designed to allow systems to be implemented with the minimum number of additional support chips. SC/MP included bus-access control signals that allowed several processors to share a common memory bus in a daisy-chained multiprocessor arrangement, or to support direct memory access hardware.

The SC/MP was followed by the SC/MP II, also known as the INS8060. National Semiconductor later introduced the 70-Series (also known as the INS8070 Series).[1][2] Some later sources refer to this family as “SC/MP III” or “SC/MP-3”,[3] terminology not used in contemporary National Semiconductor documentation.[1][2]

Designed to be as low-cost as possible, the SC/MP emphasized simple control logic and built-in multiprocessor bus arbitration. It is significantly slower than contemporary designs like the Intel 8080 or MOS 6502.[a] Another oddity was that the program counter could only increment the lower 12-bits of the 16-bit address; the upper 4-bits had to be set using special instructions. The result was that instructions accessed main memory as sixteen 4 KB "pages" and reaching memory outside those pages required multiple instructions.

The combination of slow speed and paged memory limited its attractiveness outside the embedded markets it was aimed at, and in this market it competed against the Fairchild F8 which had a number of useful additional features and cost less than a dollar more at 100-unit quantities. The system saw relatively little use. Signetics was identified as an authorized second source and published SC/MP II documentation, but it is unclear whether it manufactured any SC/MP devices.

Design

NS SC/MP registers
Main registers
76543210(bit position)
ACAccumulator
EExtension
Pointer registers
15141312111009080706050403020100(bit position)
page field
bits 15–12		12-bit address within page
bits 11–0
P0/PCProgram Counter
P1Pointer 1
P2Pointer 2
P3Pointer 3
Status Registers
76543210(bit position)
CY/LOVSBSAIEF2F1F0Status Register (SR)

ALU and main registers

The arithmetic logic unit (ALU) is accumulator-based, with a single 8-bit accumulator, AC.

A second 8-bit register, "Extension", or E, can be used as a backup for AC. E cannot be accessed directly by most instructions; data cannot be loaded directly from memory into E. Instead, National Semiconductor described the Extension Register instructions as a group of eight single-byte instructions operating between E and AC. Two transfer/exchange instructions, LDE and XAE, load AC from E and exchange AC with E respectively. The remaining six instructions use E in ALU operations on AC: ANE (AND), ORE (OR), XRE (exclusive OR), DAE (decimal add), ADE (binary add), and CAE (complement and add). Thus, for example, addition to AC can use a memory operand, an immediate operand, or E. If E is not being used for other operations, it can also be used as a temporary store for AC, for example during an interrupt.[4][5] This use as a temporary store is loosely comparable to the alternate register set of processors such as the Zilog Z80.

A major purpose of E is to act as a buffer for the built-in serial I/O system.[6][7] The SIO instruction shifts the Extension Register (E) right one bit. The least-significant bit is output on the SOUT pin while a new bit from the SIN pin is shifted into the most-significant bit. Repeated executions can transfer an entire byte serially.[8]

Once a complete 8-bit value has been read into E, it can be moved to memory by exchanging E with AC and then storing AC. For output, the reverse process can be used to load E before repeated executions of SIO.[4] Because E can be used as the second operand in logical operations on AC, a status byte read serially into E can be tested by applying a mask in AC with AND.[9]

The E register can also be substituted for the signed displacement in PC-relative, indexed, and auto-indexed memory reference instructions. If the displacement is -128 (0x80), the contents of E are used as the displacement and added to the selected pointer register (P0–P3) to form the effective address.[10][11]

The separate Status Register (SR) is 8 bits wide. The three least-significant bits, 0 through 2, are connected directly to output pins, providing an easy way to output single bits.[4] A further two pins, Sense A and Sense B, are connected to bits 4 and 5. When interrupts are enabled, Sense A serves as the interrupt request input (see details below).[12] Interrupts can be disabled by setting bit 3, Interrupt Enable (IE), to 0 with the Disable Interrupt instruction, DINT, and enabled with IEN; the Status Register can also be transferred to and from AC and manipulated there. Sense B is an additional single bit input. Bits 6 and 7 are the overflow flag and carry/link flag.[13] Although there is no explicit zero flag, zero is determined from the current content of AC.

Addressing and index registers

Like most 8-bit microprocessors of the era, the SC/MP is based around a 16-bit address bus and an 8-bit data bus. To reduce pin count, the external address bus contains only 12 pins, multiplexing 4 pins on the data bus to create a complete 16-bit address.[7] The processor only directly modifies the lower 12-bits of the program counter. There are separate instructions to set the upper four bits by copying an 8-bit value into the high byte. This provides a memory map of sixteen four-kilobyte pages. Program code cannot refer to code or PC-relative data outside its own page.[10] This leads to a curiosity of the design: when the program counter reaches the end of a page, it does not move to the next page, it returns to the start of the current page.[7]

Addressing was further limited by the two-byte instruction format, which used one byte for the opcode and a second one to indicate an offset between -128 and +127, which was added to a value in a register to produce a 12-bit address. For instance, an address might refer to a location in memory by saying it is +10 locations from the value in the program counter, or +10 from the value in one of the 16-bit index registers. To access a location outside that range, the page has to be explicitly stored in one of the index registers.[10] Because the registers are 16-bit, and the accumulator that loads values is 8-bit, setting a complete address requires several instructions.[14]

As indexes were critical to the addressing model, the SC/MP included four index registers, the "Pointer Registers" P0 through P3. P0 was the program counter, and not normally manipulated by user programs. By convention, P1 was normally used as a pointer into ROM, P2 into RAM, and P3 was used to store an address during interrupts and subroutine calls.[13] The SC/MP did not have a hardware stack or dedicated stack pointer for storing return addresses. Subroutine linkage instead used pointer registers, especially P3 with the XPPC instruction, so nested calls or interrupt handling required return addresses to be saved explicitly, or by a software stack convention.[15][16][14]

There were four primary addressing modes, PC-relative, indexed, immediate (meaning a constant in the instruction's second byte as opposed to an offset), and auto-indexed. PC-relative addressing was actually the same as indexed, selecting P0 as the index register.[10]

Auto-indexing aids in the construction of loops. If the displacement is less than zero, the contents of the Pointer Register is decreased by the displacement before the contents of the effective address are fetched or stored. If the displacement is equal to or greater than zero, the contents of the Pointer Register are used as the effective address, and the contents of the Pointer Register are increased by the displacement after the contents of the effective address are fetched or stored. This removes the need for a separate instruction to change the value in the register, so one could store the starting value of a block of data in memory in a pointer register and then loop through all of the data by calling a single instruction.[10] If the offset is negative, @-1(P2), it performs the decrement before accessing the final value. If it is positive. @1(P2), it does a post-increment.[14] This predecrement-postincrement behavior makes it possible to create a LIFO stack. Top of stack is accessed with (P2).

Interrupt handling

The system includes automatic handling of interrupts on the Sense A line. When an interrupt is received and IE is high (enabled), before starting to fetch the next instruction the system instead clears IE to prevent another interrupt, and then exchanges the values in PC and P3 using XPPC. This has the effect of saving the return address in P3 and sending the next instruction into the interrupt handler entry point previously stored in P3.[17]

The system does not include the equivalent of a return-from-interrupt. This can be performed with another XPPC, copying the previously-saved address in P3 back to the PC and execution continues where it left off. However, this leaves the wrong address in P3, not the start of the interrupt handler, but the end. To address this, the common solution is to place the XPPC that returns to the main code one instruction above the handler entry point, rather than at the end. When the handler completes, it jumps back to this instruction, so when XPPC is executed, the PC is pointed one location before the proper entry point. Because the system increments the PC before calling an instruction, this means the next interrupt will result it in entering at the correct entry point. This "exit handler" normally also sets the IE to 1 to re-enable interrupts.[18]

Interrupt latency is not quick. When an interrupt is encountered, the SC/MP requires 17 instructions generating 26 bytes of object code to save its status. The older Intel 8080 requires just four instructions generating four bytes.[19]

Bus control

A feature of the SC/MP family was its bus-access logic, using bus-request, enable-input and enable-output signals. In the original PMOS SC/MP documentation these are named BREQ, ENIN and ENOUT; in SC/MP II / INS8060 documentation the corresponding active-low signals are named NBREQ, NENIN and NENOUT.[20][21] These signals supported external direct memory access (DMA) hardware and allowed multiple SC/MP processors to be connected in a daisy-chained shared-bus arrangement.[20][21] National Semiconductor's PMOS SC/MP documentation gives example DMA and multiprocessor configurations, contrasting an external DMA controller with the SC/MP's built-in bus-access logic.[20] The INS8060 datasheet documents the corresponding SC/MP II bus-access signals, NBREQ, NENIN and NENOUT, for DMA and multiprocessor use.[21] Williamson and Dale give the equivalent SC/MP II explanation in the context of the MK14.[22]

In DMA applications, data transfers between memory and a peripheral could be made without the processor being involved in the actual data transfer, apart from control functions.[23] In functional terms, a processor requested the shared bus on its bus-request line and was granted access through its enable-input line. In the PMOS SC/MP documentation, this is described as BREQ high and ENIN high; in the SC/MP II / INS8060 documentation, the corresponding active-low signals are NBREQ and NENIN.[24][21] For multiprocessor use, the processor's enable-output line was connected to the enable-input line of the next processor in the chain. While one processor controlled the bus, later processors in the chain were locked out; when it released the bus, the enable signal was passed to the next processor. If several processors requested the bus at the same time, they were served in daisy-chain priority order. National noted for the PMOS SC/MP that typically no more than three processors were used in a cascade arrangement without an external priority-logic controller.[25]

Osborne's review of the system stated: "Bus request acknowledge logic coupled with bus access priority logic makes SC/MP the slave microprocessor of choice in any multi-microprocessor application."[26] The market for such configurations appears to have been limited.[citation needed]

Osborne and Kane noted a further consequence of this bus-access design: an SC/MP external bus cycle could be suspended after it had already begun. In their terminology, this included instruction fetch, data input, and data output cycles. If ENIN was withdrawn while the CPU had access to the bus, the SC/MP address and data lines entered the high-impedance state, relinquishing the bus, while BREQ remained asserted. When ENIN was restored, the interrupted cycle would be performed. They also noted that the available SC/MP literature did not specify the exact "point-of-no-return" within the cycle: if the cycle was already nearly complete, the processor might complete it rather than suspend and restart it. This mattered because the read and write strobes, NRDS and NWDS, could in principle be repeated, causing the same data to be read or written twice.[27] The INS8060 datasheet notes special behaviour for ILD and DLD: during these read-modify-write instructions the SC/MP does not relinquish the bus between the read and write phases. If NENIN is deasserted after the load has completed, that load portion is not repeated when NENIN is reasserted.[28]

Unusual features

The SC/MP does not include a jump-to-subroutine instruction. Instead, the assembler language includes a JS macro that writes a series of instructions to implement this functionality. The macro loads the high byte of the address into AC, and then executes XPAH to move it to the high byte of a selected pointer register. It then repeats this for the low byte using XPAL. It then executes XPPC to transfer the resulting 16-bit value from the pointer register to the PC. This sequence generates five instructions, seven bytes and overwrites AC. Since XPPC exchanges the two values, the current value of the PC is thus stored into the selected pointer register, and the return-from-subroutine can be implemented with a single XPPC to copy the value back. Nested subroutines are not supported though they can be implemented with additional code.[29]

SC/MP increments the program counter before fetching the instruction, so that on reset it actually starts executing instructions from location 0001, not 0000. This also needs to be taken into account for calculating displacements, since the offset will be added to the program counter which will be still pointing to the location of the displacement and not the next instruction.

The system included a Delay instruction, DLY, which took a single parameter, P. This stopped operation for a period of 13 + (2 x P) + (2^9 x P) + (2 x AC) microcycles, which it did by continually decrementing the value in AC until it reached zero.[30] This meant it could produce a delay between 13 and 131,593 cycles.[26] This was normally used with the serial pins; a program could set the value in AC to the time it took to transmit a single bit at a given speed and then check the value of one of the flag pins to see if it was ready for the next one.[30] Osborne notes that this feature is of limited practical use, the processor is "spinning" during the delay and this could be accomplished by writing a loop.[26]

The processor was not particularly picky about timing, and in low-speed applications it did not need to use a crystal oscillator and this could be replaced with a simple capacitor instead.[31]

Implementations

The SC/MP included an internal clock oscillator. This was common in nMOS designs like the 6502, but unusual for a chip originally fabricated in P Channel MOS (pMOS). Most pMOS processors required a separate external oscillator and clock driver, so this was an advantage for this design as it eliminated the need for one external chip. This did, however, limit the speed to 1 MHz. The SC/MP-2 used N Channel MOS (nMOS) fabrication but was otherwise identical, which allowed it to be clocked at up to 4 MHz.[7]

The SC/MP family evolved through three main implementations:

  • SC/MP-1 (ISP-8A/500), clocked at 1 MHz, first implementation in pMOS. It requires both +5 volt and -7 volt power supplies for TTL compatibility.
  • SC/MP-2 (INS8060 ISP-8A/600), clocked at 4 MHz (internally 2 MHz) first nMOS version (single +5V supply)
  • 70-Series (INS807x), clocked at 4 MHz (internally 2 MHz), included variations with up to 4 KB ROM and optional onboard BASIC (NIBL).[1][2]

Second source

Signetics was identified by Osborne and Kane as an authorized second source for the SC/MP. They listed National Semiconductor as the prime source and Signetics as the authorized second source, while stating that Signetics had not actually manufactured the processor.[32]

Signetics also published its own documentation for the SC/MP II. The 1977 Signetics Bipolar/MOS Microprocessor Data Manual listed the ISP-8A/600 "Simple Cost Effective Microprocessor (SC/MP-II)" among its MOS microprocessors and included a Signetics-branded device section for the part.[33]

In the 1982 Signetics MOS Microprocessor Data Manual, the SC/MP II appeared in application-note material rather than as a standalone product data-sheet entry in the contents. Application note M22, "Interface Techniques for the 2651 PCI", included an SC/MP II interface example and cited a "Signetics SC/MP II (ISP-8A/600) Microprocessor Specification".[34]

Uses

Montgomery Elevator of Moline, Illinois, later acquired by KONE in 1994[35], used the SC/MP in its first[citation needed] microprocessor based elevator, the "MIPROM Hydro elevator-controller system" released in 1975[citation needed]. Montgomery described MIPROM as a "microprocessor elevator logic control" system[36], and a later Otis PC-board catalogue[37] identifies board MTGMP-15783 as a "CPU MIPROM SC/MP II Board". The corresponding P-15783 CPU card is illustrated in the MIPROM I troubleshooting guide[38], and a TK Elevator spare-parts listing identifies P-15783 as a refurbished Montgomery MIPROM CPU board; the board photograph in that listing shows the processor package marked "INS8060N" and "ISP-8A/600N"[39]. The MIPROM I troubleshooting guide also lists CPU card P-15783 as a replacement for P-16782, but the replaced P-16782 is not shown clearly enough to identify the processor used on P-16782.

The SC/MP was used as the basis of a single board microcontroller produced by Science of Cambridge (later Sinclair Research Ltd) called the MK14. This was based on National's own Introkit design, and National offered Sinclair a deal on completed sets which could not be matched by building their own. This allowed the MK14 to sell for the extremely low cost of £39.95.

Doug Neubauer, best known as the author of Star Raiders, had moved to Atari after working at National on a product identified only as a "home computer product".[40] This had progressed to the stage of a wire wrapped prototype before the company killed it.[41]

Example code

The following assembler source code is for a subroutine CPYMEM that copies bytes from one location to another. This routine can be used to copy between pages but cannot cross a page. It can be executed from ROM or RAM. If executing from RAM, loop counting could be accelerated with a DLD instruction using a PC-relative counter. This routine uses an unusual @1(P1) addressing mode that is used to auto-index through the memory. Unlike other processors with auto-index such as the 68000, the SC/MP auto-index stride can be larger than the datum size.

 
 
 
1000
1000 03
1001 01
1002 C5 01
1004 CE 01
1006 C4 FE
1008 70
1009 9C F6
100B 3F
            
; Copy memory words addressed by P1 to location addressed
; by P2 for a length of up to 255 bytes. Length is passed
; in AC (accumulator). Return address in P3.
        =       X'1000
CPYMEM: SCL                   ; Set carry for upcoming ADD
CPYLP:  XAE                   ; Save count in E
        LD      @1(P1)        ; Get byte to copy, inc P1
        ST      @1(P2)        ; Save save it, inc P2
        LDI     -2            ; -2 to AC to decrement
        ADE                   ; E (set carry made it -1)
        JNZ     CPYLP         ;Continue for all bytes
        XPPC    P3            ;Return to caller

Notes

  1. ^ The original SC/MP takes 11 "microcycles" to do an 8-bit add immediate (ADI) with each microcycle requiring two clocks, 22 clocks total (22µS at 1 MHz). Contemporaneous CPUs are faster: The 8080's add immediate (ADI) takes seven clocks (3.5µS at 2 MHz). A 6502 add immediate (ADC) takes two clocks (2µS at 1 MHz).

References

Citations

  1. ^ "INS8070-Series Microprocessor Family". National Semiconductor. October 1980. Retrieved 4 May 2026.
  2. ^ "70-Series Microprocessor User's Manual". National Semiconductor. 1979. Retrieved 4 May 2026.
  3. ^ "NS INS8070 - SC/MP III" (in Japanese). Semiconductor Collection Exhibition Hall. Archived from the original on 18 April 2001. Retrieved 4 May 2026.
  4. ^ Handbook 1977, p. 1.6.
  5. ^ Programming and Assembler Manual 1976, pp. 5–13.
  6. ^ Handbook 1977, pp. 1.2, 1.10.
  7. ^ Osborne & Kane 1981, p. 3.3.
  8. ^ Programming and Assembler Manual 1976, pp. 5–17.
  9. ^ Handbook 1977, p. 1.13.
  10. ^ Handbook 1977, p. 1.11.
  11. ^ Programming and Assembler Manual 1976, pp. 3–6.
  12. ^ Programming and Assembler Manual 1976, pp. 6–11.
  13. ^ Handbook 1977, p. 1.3.
  14. ^ Osborne & Kane 1981, p. 3.4.
  15. ^ Handbook 1977, pp. 1–5.
  16. ^ Williamson & Dale 1980, pp. 104–106.
  17. ^ Osborne & Kane 1981, p. 3.14.
  18. ^ Osborne & Kane 1981, p. 3.16.
  19. ^ Handbook 1977, p. C.5.
  20. ^ Technical Description 1976, pp. 2–4–2–6.
  21. ^ INS8060 Datasheet 1978, pp. 10–11.
  22. ^ Williamson & Dale 1980, pp. 183–187.
  23. ^ Handbook 1977, pp. 1–2.
  24. ^ Technical Description 1976, pp. 2–4.
  25. ^ Technical Description 1976, pp. 2–5–2–6.
  26. ^ Osborne & Kane 1981, p. 3.1.
  27. ^ Osborne & Kane 1981, pp. 3.8–3.9.
  28. ^ INS8060 Datasheet 1978, p. 10.
  29. ^ Handbook 1977, p. 1.5.
  30. ^ Handbook 1977, p. 2C3.9.
  31. ^ Handbook 1977, p. 1.1.
  32. ^ Osborne & Kane 1981, pp. 3–1.
  33. ^ Signetics 1977, pp. contents p. 5; SC/MP II section pp. 146–162.
  34. ^ Signetics 1982, pp. contents p. ii; App Note M22, pp. 6–6–6–7.
  35. ^ "History". KONE Corporation. Retrieved 5 May 2026.
  36. ^ "Miprom: Microprocessor Elevator Logic Control for the Mass Elevator Market" (Brochure). Montgomery Elevator Company. pp. 1–3. Retrieved 5 May 2026. – via KONE Spares.
  37. ^ Otis PC Board Catalog. Otis Elevator Company. November 2010. p. 73. Retrieved 5 May 2026.
  38. ^ MIPROM I Troubleshooting Guide. Montgomery Elevator Company. October 1990. pp. 14, 69. 61111-753. Retrieved 5 May 2026.
  39. ^ "Refurbished MIPROM CPU Board Montgomery P-15783". TKE Spare Parts. TK Elevator Manufacturing, Inc. Retrieved 5 May 2026.
  40. ^ Fleming, Jeffrey (September 20, 2007). "Video Games' First Space Opera: Exploring Atari's Star Raiders". Archived February 27, 2008 at the Wayback Machine. Retrieved May 28, 2024.
  41. ^ Neubauer, Doug. "The Atari Years"

Bibliography